1. Field of Invention
The present invention relates to a field of semiconductor, and particularly, to a semiconductor structure and a method of manufacturing the same. More particularly, the present invention relates to a method of manufacturing a self-aligned via stack with variable via sizes and a semiconductor structure having a self-aligned via stack with variable via sizes manufactured by said method.
2. Description of Prior Art
Metal lines above vias in IC interconnects lead to serious problems of via-to-via or via-to-line shorts as the spacing between the semiconductor devices is aggressively scaled down. Therefore, requirements for the alignment between vias and metal lines in the photolithography become stricter, resulting in higher costs for massive production. Another method is to make smaller vias, which brings higher requirements for photolithography.
A method of manufacturing a self-aligned via stack is disclosed in the present invention. The present invention is able to form the via and the metal lines at the same time. The simultaneously formed via and metal lines are referred as the via stack. This process and its problem will be described in detail in the following in conjunction with FIG. 1. FIGS. 1(a)-(d) illustrate a schematic view of manufacturing a self-aligned via stack. Such a self-aligned via stack primarily comprises an etching stop layer 1001, an interlayer dielectric (ILD) layer 1002 located on the etching stop layer, and a hard mask layer 1003 located on the ILD layer 1002. As shown in FIG. 1(a), a photoresist 1004 is applied and patterned so that the via is formed among the remaining photoresist 1004. Next, as shown in FIG. 1(b), the hard mask layer is etched to further form the via in the hard mask layer, and the remaining photoresist and the etched polymer are cleaned and removed. As shown in FIG. 1(c), after the patterning for the via is completed, a photoresist pattern 1005 is coated again on the hard mask layer to define the patterns of the metal lines to be formed. By employing the hard mask 1003 on the ILD layer 1002 and the photoresist pattern 1005 as the mask, it is further etched into the ILD layer 1002. The via formed by etching is shown in FIG. 1(d), and the width of the upper portion of the via is greater than that of the lower portion. Finally, a conductive plug is formed in the formed via. The upper potion of the conductive plug is wider and is used as the metal lines, and the lower portion of the conductive plug is narrower and is used as a conductive plug in the silicon via and commonly is electrically connected to the interconnect structure on the semiconductor structure. Thus, the via stack structure is formed by the self-alignment technique.
However, because the size of the via may not be altered arbitrarily, there is still a problem of shorts for the self-aligned via stack structure as shown in FIG. 1.